A Bound on the Moments of a TTL-based Cache’s Miss-Process

Due to the omnipresence of caching in modern computing and networks, characterizing the performance of caches is an important aspect of system performance and scalability analysis. While even analytical models for single caches proved to be challenging, nowadays, many configurations already encompass hierarchies of caches. Time-to-live (TTL) based caches have recently been proposed as a general approach to simplify performance analysis of caching networks. Previous work has used approximation and recursion techniques to characterize the inter-miss process which is essential to study this setting. This work introduces an appropriate mathematical abstraction of the cache model as a martingale representation. We derive explicit bounds on all moments of the inter-miss time of a TTL-based cache and report preliminary simulation results. Our approach does not rely on recursion techniques but is still general enough to capture different previously introduced TTL-based caching models.